Profile
International Journal of Computer & Software Engineering Volume 4 (2019), Article ID 4:IJCSE-146, 7 pages
https://doi.org/10.15344/2456-4451/2019/146
Review Article
Performance Assessment of an Efficient Search and Realization Technique of the S-Box in the AES Cryptosystem

Mostafa Abd-El-Barr

Department of Information Science (ISC), College of Computing Sciences and Engineering (CCSE), Kuwait University, Safat 13060, Kuwait
Prof. Mostafa Abd-El-Barr, Department of Information Science (ISC), College of Computing Sciences and Engineering (CCSE), Kuwait University, Safat 13060, Kuwait; E-mail: mostafa.abdelbarr@gmail.com
23 March 2019; 23 May 2019; 25 May 2019
Abd-El-Barr M (2019) Performance Assessment of an Efficient Search and Realization Technique of the S-Box in the AES Cryptosystem. Int J Comput Softw Eng 4: 146. doi: https://doi.org/10.15344/2456-4451/2019/146

References

  1. Rao S, Mahto D, Khan DA (2017) A Survey on Advanced Encryption Standard. IJSR 6: 710-723. View
  2. Nechvatal J, Barker E, Bassham L, Burr W, Dworkin M, et al. (2001) Report on the Development of the Advanced Encryption Standard (AES). J Res Natl Inst Stand Technol 106: 511-577. View
  3. Padate R, Patel A (2014) Encryption and decryption of text using AES algorithm. International Journal of Emerging Technology and Advanced Engineering 4: 833-859. View
  4. Samiee H, Atani RE, Amindavar H (2011) A novel area-throughput optimized architecture for the AES algorithm. International Conference on Electronic Devices, Systems and Applications (ICEDSA). View
  5. Rahman T, Pan S, Zhang Q (2010) Design of a High Throughput 128-bit AES (Rijndael Block Cipher). International Multi Conference of Engineers and Computer Scientists. View
  6. Hodjat A, Verbauwhede I (2006) Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. IEEE Transactions on Computers 55: 366-372. View
  7. Tillich S, Feldhofer M, Großschädl J (2006) Area, delay, and power characteristics of standard-cell implementations of the AES S-box. Embedded Computer Systems: Architectures, Modeling, and Simulation, Springer Verlag 4017: 457-466. View
  8. McLoone M, McCanny JV (2001) High performance single-chip FPGA Rijndael algorithm implementations, Cryptographic Hardware and Embedded Systems (CHES 2001). Springer Verlag 2162: 65-76. View
  9. Pipeline AES S-box Implementation Starting with Substitution Table, LC Engineers Inc., USA. View
  10. Abd-El-Barr M, Al-Farhan A (2014) A Highly Parallel Area Efficient S-Box Architecture for AES Byte-Substitution. International Journal of Engineering and Technology 6: 346-350. View
  11. Specialty Process 0.35μm CMOS Application Notes. View
  12. Satoh A, Morioka S, Takano T, Munetoh S (2001) A compact rijndael hardware architecture with S-box optimization. Advances in Cryptology - ASIACRYPT 2248: 239-254. View
  13. Wolkerstorfer J, Oswald E, Lamberger M (2002) An ASIC implementation of the AES SBoxes. Topics in Cryptology-CT-RSA 2002: 67-78. View
  14. Canright D (2005) A very compact S-Box for AES. Cryptographic Hardware and Embedded Systems-CHES. Springer Verlag. View
  15. Bertoni G, Macchetti M, Negri L (2004) Power-efficient ASIC Synthesis of Cryptographic Sboxes. ACM Creat Lakes symposium on VLSI. View