A Low-Energy Multi-Threaded Processor Design for Application Specific Embedded Systems : Table 7

Table 7: CPI regression data over varied memory size.

Cache Assoc.	Cache Size (B)	App.	ST			MT			MT-Sync
Cache Assoc.	Cache Size (B)	App.	Avg.	Slope X 10³	Reg. Error	Avg.	Slope X 10³	Reg. Error	Avg.	Slope X 10³	Reg. Error
1-way	128	DCT	2.45	3.1	0.0153	2.57	2.4	0.4126	1.20	0.3	0.0648
		MM	1.78	1.6	0.0082	2.28	5.8	0.5322	1.13	0.3	0.0106
		MI	1.33	0.7	0.0035	2.26	7.0	0.0070	1.02	0.1	0.0001
		LU	2.64	3.5	0.0172	2.70	4.1	0.4588	1.94	0.9	0.1689
		CHL	1.17	0.4	0.0018	3.65	12.4	0.8176	1.06	0.1	0.0149
		GE	1.72	1.5	0.0076	2.90	6.1	0.2577	2.14	3.8	0.2805
		RS	3.53	5.5	0.0435	1.81	1.1	0.1664	1.51	0.8	0.1600
	256	FFT	1.56	1.2	0.0060	1.98	3.4	0.0557	1.33	0.9	0.0373
	256	LE	2.78	3.8	0.0188	1.53	1.1	0.0683	1.40	1.0	0.0641
	512	AES	1.99	2.1	0.0104	1.36	0.5	0.0852	1.16	0.4	0.0228
	AVG		2.09	2.3	0.0132	2.31	4.4	0.2862	1.39	0.9	0.0824
2-way	128	DCT	2.45	5.2	0.0258	2.57	2.6	0.2179	1.20	0.5	0.0465
		MM	3.08	4.4	0.0219	1.45	1.5	0.0351	1.13	0.3	0.0102
		MI	1.33	0.7	0.0035	1.23	0.6	0.0006	1.03	0.1	0.0001
		LU	3.38	5.0	0.0248	1.90	1.0	0.2446	1.51	0.3	0.0706
		CHL	3.31	4.9	0.0243	1.20	0.4	0.0322	1.07	0.1	0.0108
		GE	3.67	5.7	0.0283	1.97	2.4	0.0605	1.56	1.2	0.0549
		RS	3.50	5.3	0.0264	1.82	1.5	0.0578	1.48	1.0	0.0957
	256	FFT	3.00	4.2	0.0211	1.62	2.3	0.0642	1.28	0.9	0.0432
	256	LE	2.99	4.2	0.0210	1.37	1.3	0.0421	1.32	1.1	0.0414
	512	AES	2.45	3.1	0.0153	1.09	0.4	0.0253	1.12	0.4	0.0273
	AVG		2.97	4.4	0.0219	1.68	1.5	0.0839	1.29	0.6	0.0415