Table 6: CPIs of banchmark LE under 128 byte instruction cache.
IM Size | ST | MT | MT-sync |
(MB) | 1-way | 2-way | 1-way | 2-way | 1-way | 2-way |
50 | 2.19 | 2.57 | 2.19 | 1.40 | 1.33 | 1.21 |
100 | 2.52 | 2.85 | 1.98 | 1.38 | 1.43 | 1.24 |
150 | 2.63 | 3.14 | 2.20 | 1.55 | 1.44 | 1.28 |
200 | 2.85 | 3.43 | 2.60 | 1.75 | 1.77 | 1.41 |
250 | 3.07 | 3.71 | 2.47 | 1.68 | 1.64 | 1.44 |
300 | 3.29 | 4.00 | 3.21 | 1.84 | 1.86 | 1.58 |
350 | 3.62 | 4.43 | 3.76 | 2.07 | 1.92 | 1.60 |
400 | 3.84 | 4.72 | 4.03 | 2.35 | 2.36 | 1.92 |
450 | 4.06 | 5.00 | 3.92 | 2.43 | 2.09 | 1.77 |
500 | 4.28 | 5.29 | 4.83 | 2.48 | 2.22 | 1.86 |
Reg. Error | 0.0356 | 0.0031 | 0.0222 | 0.0071 | 0.0087 | 0.0048 |
Slope | 0.0046 | 0.0062 | 0.0062 | 0.0027 | 0.0022 | 0.0016 |
Average | 3.24 | 3.91 | 3.12 | 1.89 | 1.81 | 1.53 |