A Low-Energy Multi-Threaded Processor Design for Application Specific Embedded Systems : Table 5

Table 5: Comparison of area cost of MT and MT-sync processor designs.

	Cache Configuration
	128 Byte Cache		256 Byte Cache		512 Byte Cache
	1-way	2-way	1-way	2-way	1-way	2-way
Area of MT (μm²)	200349	201704	213250	215049	238684	241378
Area of MT-Sync (μm²)	208863	210187	222134	223709	248539	250680
Area Increase (%)	4.25	4.21	4.17	4.03	4.13	3.85